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Integrated Circuit Systems, Inc.
ICS9342
133MHz Clock Generator and Integrated Buffer for PowerPCTM
Recommended Application: Power PC System Clock Output Features: * 12- CPUs @ 3.3V, up to 146MHz * 1- PCIREF @ 3.3V, up to 73MHz * 1 - OUT 3.3V, 64MHz * 1 - OUT/2 3.3V, OUT/2MHz * 2 - REF @ 3.3V, 14.318MHz Features: * Up to 146MHz frequency support * Support power management: CPU, PCI stop and power down mode. * Spread spectrum for EMI control (0 to -0.5%, 0.25%). * Uses external 14.318MHz crystal * FS pins for frequency select * Support for industrial temperature range (-40C to 85C) Key Specifications: * CPU Output Skew: <200ps * CPU - PCI Output Skew: <500ps * CPU Output Jitter: <150ps * PCI Output Jitter: <500ps
Pin Configuration
VDDREF REF1 REF0 GNDREF X1 X2 *PD# *CPU-STOP# VDD GND *PCI_STOP# *SS_EN# VDDPCI PCIREF GNDPCI *FS0 *FS1 *FS2 VDDFP GNDFP *TEST#/OUT *BOOST#/OUT_DIV2 *PDFP# VDDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 OUTSEL1* VDDCPU GNDCPU CPU0 CPU1 CPU2 VDDCPU GNDCPU CPU3 CPU4 CPU5 VDDCPU GNDCPU CPU6 CPU7 CPU8 VDDCPU GNDCPU CPU9 CPU10 CPU11 VDDCPU GNDCPU OUTSEL0*
48-Pin 300mil SSOP
* Internal pull-up resistor of 120K to VDD on indicated inputs.
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum OUT OUT/DIV2
Functionality
TEST 1
2
ICS9342
CPU MHz 133.33 100.00 83.33 66.66 133.33 100.00 83.33 66.66
FS2 1 1 1 1 0 0 0 0
FS1 1 1 0 0 1 1 0 0
FS0 1 0 1 0 1 0 1 0
PCI MHz 33.33 33.33 33.33 33.33 66.66 66.66 66.66 66.66
REF MHz 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
REF (1:0)
1 1 1 1 1
CPU DIVDER
Stop
12
CPUCLK (11:0)
OUTSEL (1:0) SS_EN# Control Logic FS (2:0) PD# PDFP# TEST# BOOST#
PCI DIVDER Stop
PCIREF
1 1
Config. Reg.
9342 Rev E 9/06/00 Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9342
General Description
The ICS9342 generates all clocks required for high speed PowerPC RISC microprocessor systems. With a zero delay buffer chip such as the ICS9112-17 multiple PCI clock outputs can be generated in phase with PCIREF. Spread Spectrum may be enabled by driving the SS_EN# pin low. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9342 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Pin Configuration
PIN NUMBER 1 2,3 4 5 6 7 8 9 10 11 12 13 14 15 18, 17, 16 19 20 21 PIN NAME VDDREF REF[1:0] GNDREF X1 X2 PD# CPU_STOP# VDD GND PCI_STO P# SS_EN# VDDPCI PCIREF GNDPCI FS (2:0) VDDFP GNDFP O UT TEST# OUT_D IV2 BOOST# PDFP# VDDA OUTSEL(1:0) GNDCPU VDDCPU TYPE PWR OU T PWR IN OU T IN IN PWR PWR IN IN PWR OU T PWR IN PWR PER OU T IN OU T IN IN PWR IN PWR PWR DESCRIPTION Ref(1:0), XTAL power supply, nominal 3.3V 14.318 M Hz reference clocks Ground pin for the REF outputs Crystal input,nominally 14.318M Hz. Crystal output, nominally 14.318M Hz. Pow ers down chip, active low . Stops all CPUCLKs [11:0] at logic 0 level, w hen input low 3.3V power for the digital core. Ground pin for the digital core. Drives PCIREF to logic 0 level, when input low Spread spectrum is turned on by driving this input low and turned off by driving it high. Pow er supply for PCIREF, nominal 3.3V. Reference clock for PCI Zero Delay Buffer. Ground pin for PCIREF. Frequency select pins. 3.3V power for the Fixed PLL core. Ground pin for the Fixed PLL core. 3.3V O UT reference clock. Logic input to select over clocking or under clocking frequencies. (latched input) 3.3V 1/2 frequency OUT reference clock. Logic input to select normal or test mode frequencies. (latched input) Pow ers down Fixed PLL. When driven to low, OUT and OUT_DIV2 clocks will be stopped 3.3V power for the PLL core Frequency select pins for OUT and OUT_DIV2 clocks. Ground pin for CPU clocks. 3.3V power supply for CPU clocks.
22 23 24 48, 25 26, 31, 36, 41, 46 27, 32, 37, 42, 47
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2
ICS9342
Frequency Selection
BOOST# X X X X X X X X 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 TEST# 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FS2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 FS1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 FS0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CPU MHz 133.33 100.00 83.33 66.66 133.33 100.00 83.33 66.66 146.62 109.99 91.58 73.31 146.62 109.99 91.58 73.31 119.98 90.00 74.93 119.98 90.00 74.93 PCI MHz 33.33 33.33 33.33 33.33 66.66 66.66 66.66 66.66 36.6 36.6 36.6 36.6 73.3 73.3 73.3 73.3 30.00 30.00 30.00 60.00 60.00 60.00 REF MHz SS TYPE/VALUE If SS enabled
14.318 0 to -0.5% Down Spread 14.318 0 to -0.5% Down Spread 14.318 0 to -0.5% Down Spread 14.318 0 to -0.5% Down Spread 14.318 0 to -0.5% Down Spread 14.318 0 to -0.5% Down Spread 14.318 0 to -.5% Down Spread 14.318 0 to -0.5% Down Spread 14.318 + 0.25% Center Spread 14.318 + 0.25% Center Spread 14.318 + 0.25% Center Spread 14.318 + 0.25% Center Spread 14.318 + 0.25% Center Spread 14.318 + 0.25% Center Spread 14.318 + 0.25% Center Spread 14.318 + 0.25% Center Spread 14.318 + 0.25% Center Spread 14.318 + 0.25% Center Spread 14.318 + 0.25% Center Spread 14.318 + 0.25% Center Spread 14.318 + 0.25% Center Spread 14.318 + 0.25% Center Spread
Test Mode, CPU=Ref/4, PCI=Ref/8
Tristate, all outputs
OUT_SEL1 1 1 0 0
OUT_SEL0 1 0 1 0
OUT (MHz) 48 40 64 48
OUT_DIV2 (MHz) 24 20 32 48#
REF (MHz) 14.318 14.318 14.318 14.318
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3
ICS9342
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . -40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5% (unles s otherwis e s tated) PARAM ETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance 1 Transition Time Settling Time 1 Clk Stabilization Skew1
1 1
SYM BOL VIH VIL IIH IIL1 IIL2 IDD3.3 OP6 6 IDD3.3 OP8 3 IDD3 .3OP1 0 0 IDD3 .3OP1 3 3 IDD3.3P D Fi C IN C INX T Tran s TS T STAB tCP U -P CI
CONDITIONS
M IN 2 VSS -0.3 -5 -200
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors Select @ 66M Hz; M ax discrete cap loads Select @ 83M Hz; M ax discrete cap loads Select @ 100M Hz; M ax discrete cap loads Select @ 133M Hz; M ax discrete cap loads PD# = 0 VDD = 3.3 V Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. VT = 1.5 V
0.1 2.0 -100 134 165 198 254 313
M AX UNITS VDD+0.3 V 0.8 V A 5 A A 175 200 mA 225 300 400 16 5 22.5 3 A M Hz pF pF ms ms 3 500 ms ps
12 13.5
14.318 18 1 190
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4
ICS9342
Electrical Characteristics - CPU
T A = 0 - 70 C; V DD = 3.3 V +/-5%; C L = 20 pF (unless otherwise stated) PARAM ETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Cycle-to-cycle
1
SYM BOL RDSP 2 B
1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -8.0 mA IOL = 12 mA VOH =1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V; Cpu@ 66M , 83M , 100M VT = 1.5 V; Cpu@133M & 146.6M VT = 1.5 V VT = 1.5 V; Normal VT = 1.5 V; Spread, CPU = 91.58M Hz VT = 1.5 V; Spread, CPU remaining freq.
M IN 13.5 13.5 2
TYP 20 29 2.4 0.32 -37 26 1.13 1.27 52 56 187 95 143 143
M AX 45 45 0.4 -16 2 2 56 60 200 150 200 175
UNITS V V mA mA ns ns % ps ps
RDSN2B VOH2 B VOL2 B IOH2 B IOL2B t r2 B
1
19
t f2 B 1 d t2 B 1 t sk 2 B 1 tj cy c-cyc2 B 1
45 51
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70 C; VDD = 3.3 V +/-5%; CL =30 pF PARAMETER SYMBOL Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time
1
CONDITIONS
MIN 12 12 2.4
TYP 21 21.2 0.17 -60 47 1 0.9 50 170
MAX UNITS 55 55 0.4 -22 2 2 55 500 V mA mA ns ns % ps
RDSP1
1 1
VO = VDD*(0.5) VO = VDD*(0.5) IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
RDSN1 VOH1 VOL1 IOH1 IOL1 tr1 tf1
25 0.5 0.5 45
Fall Time1 Duty Cycle1 Jitter, Cycle-to-cycle1
1
dt1 tjcyc-cyc1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
5
ICS9342
Electrical Characteristics - REF, OUT , OUT /2
T A = 0 - 70 C; V DD = 3.3 V +/-5%; C L = 20 pF (unless otherwise stated) PA RA M ETER Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Ris e Time REF Fall Time
1 1 1
SYM BOL RDSP 5
1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -12 mA IOL = 10 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V; OUT VOH = 2.4 V, VOL = 0.4 V; OUT VT = 1.5 V; OUT VOL = 0.4 V, VOH = 2.4 V; OUT/2 VOH = 2.4 V, VOL = 0.4 V; OUT/2 VT = 1.5 V; OUT/2 VOL = 0.4 V, VOH = 2.4 V; REF VOH = 2.4 V, VOL = 0.4 V; REF VT = 1.5 V; REF VT = 1.5 V; OUT, OUT/2 VT = 1.5 V; REF
M IN 20 20 2.4
TYP 34 31 2.9 0.33 -30 23 1.8 2 52 2.2 2.1 50 2.7 2.8 50 280 450
M A X UNITS 60 60 0.4 -20 4 4 55 4 4 55 4 4 55 500 1000 V V mA mA ns ns % ns ns % ns ns % ps ps
RDSN5 VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 tr5 tf5
1
16 1.5 1.5 45 1.5 1.5 45 1.5 1.5 45
Duty Cycle Ris e Time OUT Fall Time
1
1
Duty Cycle Ris e Time OUT/2 Fall Time
1
dt5 tr5 tf5 dt5 tjcyc-cyc5 t jcy c-cy c5
1
Duty Cycle Jitter, Cycle-to-cycle1 Jitter, Cycle-to-cycle 1
1
1
Guaranteed by des ign, not 100% tes ted in production.
Third party brands and names are the property of their respective owners.
6
ICS9342
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9342 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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7
ICS9342
Power Management
PD# 1 1 0 0 PDFP# 1 0 1 0 OUT1, OUT_DIV2 RUNNING STOPPED STOPPED STOPPED CPU, PCI, REF RUNNING RUNNING STOPPED STOPPED
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. The REF and OUT clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPU
PCIREF VCO Crystal
Notes: 1. All timing is referenced to the Internal CPU (defined as inside the ICS9342 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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8
ICS9342
CPU_STOP# Timing Diagram
CPU_STOP# is an asynchronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI clock (and hence CPU clock) and must be internally synchronized to the external output. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks must always be stopped in a low state and started in such a manner as to guarantee that the high pulse width is a full pulse.
CPUCLK
(internal)
PCICLK
(internal)
CPU_STOP# PCI_STOP# PD# CPUCLK
(externall)
Notes:
1. All timing is referenced to the internal CPUCLK. 2. The internal label means inside the chip and is a reference only. This in fact may not be the way that the control is designed. 3. PD# and PCI_STOP# are shown in a high state.
PCI_STOP# Timing Diagram
PCI_STOP# is an input to the clock synthesizer. It is used to turn off the PCIREF clock for low power operation. PCIREF clock is required to be stopped in a low state and started such that a full high pulse width is guaranteed.
CPUCLK
(internal)
PCICLK
(internal)
CPU_STOP# PCI_STOP# PD#
PCIREF
(externall)
Notes: 1. All timing is referenced to CPUCLK. 2. Internal means inside the chip. 3. All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a high state.
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9
ICS9342
SYMBOL
In Millimeters COMMON DIMENSIONS MIN MAX 2.413 0.203 0.203 2.794 0.406 0.343
In Inches COMMON DIMENSIONS MIN MAX .095 .008 .008 .110 .016 .0135
A A1 b c D E E1 e h L N VARIATIONS N 28 34 48 56 64
0.127 0.254 SEE VARIATIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE VARIATIONS .395 .291 .015 .420 .299 .025
0.635 BASIC 0.508 1.016 SEE VARIATIONS 0 8
0.025 BASIC .020 .040 SEE VARIATIONS 0 8
D mm. MIN 9.398 11.303 15.748 18.288 20.828 MAX 9.652 11.557 16.002 18.542 21.082 MIN .370 .445 .620 .720 .820
D (inch) MAX .380 .455 .630 .730 .830
Ordering Information
ICS9342yF-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
10
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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